This invention relates to automation of logic designing in IC, LSI. In the trend of large scale and high integration represented by VLSI, it is an urgent problem to reduce the manpower required in development and to eliminate the chronic shortage of designers. These matters are expected to be solved by development of various CAD tools, but as for the logic designing, at the present, many subjects are left unsolved before realization.
For example, when automatically translating from the hardware descriptive language into a logic circuit, the following problems were experienced in the conventional system.
(1) The hardware description language that can be processed is fixed.
The conventional system, was designed to translate only a specific description language. Therefore, when the description language was changed, the program had to be drastically revised.
(2) Abstract expressions cannot be used in circuit operation.
The hardware description languages are classified by the structural level, functional level and behavioral level used in describing a circuit. In the conventional description language translator model, the structural level was mostly used because it was possible to correspond directly to the circuit. The output called net list obtained with respect to more abstract description such as functional level and behavioral level was inferior in quality as compared with that obtained manually.
(3) Translation is effected while leaving the redundancy of description as it is.
As one of the causes of the poor quality of the result of translation from the description of the functional or higher level indicated in (2), translation together with the remaining redundancy may be listed. In the functional design which is a step before logic design, the designer puts the first emphasis on realization of function of desired circuit. Therefore, as for the redundancy for expressing this function, the designer pays little attention to redundant expression, assuming that it will be eliminated in the logic designing state. In a simple serial translation algorithm, since the redundancy of expression is not taken into consideration, multiple portions having same functions are present within a same circuit.
(4) The intent of the designer is not expressed in the result of output.
When realizing a function expressed in a description language in a circuit, many selection limb may be present. In such a case, the designer selects a most practical means depending on the case, but in the conventional system, practically, only a preprogrammed method could be selected, and it was difficult to express the intent of the designer in the circuit.